View MAX111BEWE_8628625.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ________________________________________________________________ maxim integrated products 1 ge ne ra l de sc ript ion the max110/max111 analog-to-digital converters (adcs) use an internal auto-calibration technique t o achieve 14-bit resolution plus overrange, with no e xter- nal components. operating supply current is only 550a (max110) and reduces to 4a in power-down mode, making these adcs ideal for high-resolution b at- tery-powered or remote-sensing applications. a fast serial interface simplifies signal routing and opto -isola- tion, saves microcontroller pins, and offers compat ibility with spi?, qspi?, and microwire?. the max110 operates with 5v supplies, and converts differenti al analog signals in the -3v to +3v range. the max111 operates with a single +5v supply and converts diff er- ential analog signals in the 1.5v range, or single - ended signals in the 0v to +1.5v range. internal calibration allows for both offset and gai n-error correction under microprocessor (p) control. both devices are available in space-saving 16-pin dip an d so packages, as well as an even smaller 20-pin ssop package. ________________________applic a t ions process control weigh scales panel meters data-acquisition systems temperature measurement ____________________________fe a t ure s ? single +5v supply (max111) ? two differential input channels ? 14-bit resolution plus sign and overrange ? 0.03% linearity (max110)0.05% linearity (max111) ? low power consumption: 550a (max110)640a (max111) 4a shutdown current ? up to 50 conversions/sec ? 50hz/60hz rejection ? auto-calibration mode ? no external components required ? 16-pin dip/so, 20-pin ssop orde ring i nform a t ion 19-0283; rev 5; 11/98 typic a l ope ra t ing circ uit pin configura t ions in1+ in1- ref+ ref- cs rcsel sclk din dout in2+ in2- v dd +5v -5v (0v) from c max110 max111 ( ) are for max111 v ss (agnd) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 in1+ ref- ref+ v dd rcsel xclk sclk busy in1- in2+ in2- v ss (agnd) gnd din dout cs top view max110 max111 dip/so ( ) are for max111 part max110 acpe max110bcpe max110acwe 0c to +70c 0c to +70c 0c to +70c temp. range pin-package 16 plastic dip 16 plastic dip 16 wide so max110bcwe 0c to +70c 16 wide so max110acap 0c to +70c 20 ssop max110bcap 0c to +70c 20 ssop evaluation kit available max110bc/d 0c to +70c dice* ordering information continued at end of data sheet. * contact factory for dice specifications. spi and qspi are trademarks of motorola, inc. micro wire is a trademark of national semiconductor corp. pin configurations continued at end of data sheet. inl(%) 0.03 0.05 0.03 0.05 0.03 0.05 0.05 for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 2 _______________________________________________________________________________________ absolute maximum ratings v dd to gnd ............................................. ..............................+6v v ss to gnd (max110).................................... ..........+0.3v to -6v agnd to dgnd....................................... ..............-0.3v to +0.3v v in1+ , v in1- ......................................(v dd + 0.3v) to (v ss - 0.3v) v in2+ , v in2- ......................................(v dd + 0.3v) to (v ss - 0.3v) v ref+ , v ref- ....................................(v dd + 0.3v) to (v ss - 0.3v) digital inputs and outputs ......................... (v dd + 0.3v) to -0.3v continuous power dissipation 16-pin plastic dip (derate 10.53mw/c above +70c). ....842mw 16-pin wide so (derate 9.52mw/c above +70c) ...... 762mw 20-pin ssop (derate 8.00mw/c above +70c) ......... ..640mw 16-pin cerdip (derate 10.00mw/c above +70c)...... 800mw operating temperature ranges max11_ _c_ _....................................... ...............0c to +70c max11_ _e_ _....................................... ............-40c to +85c max11_bmje ......................................... ........-55c to +125c storage temperature range .......................... ...-65c to +160c lead temperature (soldering, 10sec) ................ .............+300c stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. electrical characteristicsmax110 (v dd = 5v 5%, v ss = -5v 5%, f xclk = 1mhz, 2 mode (dv2 = 1), 81,920 clk cycles/conv, v ref+ = 1.5v, v ref- = -1.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) lsb na 500 conditions i in+ , i in- input bias current (note 3) pf 10 -0.83 x v ref v in 0.83 x v ref -v ref v in v ref -0.83 x v ref v in 0.83 x v ref input capacitance -v ref v in v ref v v ss +v dd - 2.25 2.25 v in+ , v in- absolute input voltage range v -v ref +v ref v in differential input voltage range ppm 30 power-supply rejection 15 ppm/c 8 full-scale error temperature drift % 0.1 v/c 0.003 offset error temperature drift (note 6) units min typ max symbol parameter mv 4 offset error 0.018 0.03 0.06 0.015 0.03 0.04 v in+ = v in- = 0v max110bc/e max110ac/e after gain calibration (note 5) after offset null v ss = -5v, v dd = 4.75v to 5.25v v dd = 5v, v ss = -4.75v to -5.25v (notes 3, 4) 2 dnl differential nonlinearity ppm/v 6 cmrr common-mode rejection ratio -2.5v (v in+ = v in- ) 2.5v uncalibrated -8 0 full-scale error uncalibrated 0.02 -v ref v in v ref -0.83 x v ref v in 0.83 x v ref %fsr inl relative accuracy (notes 3, 5C7) 0.1 0.05 max110bm (note 2) 14 + pol + ofl res resolution bits no-missing-codes resolution (note 3) 13 + pol + ofl bits accuracy (note 1) analog inputs downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs _______________________________________________________________________________________ 3 electrical characteristicsmax110 (continued) (v dd = 5v 5%, v ss = -5v 5%, f xclk = 1mhz, 2 mode (dv2 = 1), 81,920 clk cycles/conv, v ref+ = 1.5v, v ref- = -1.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) v v 4.75 5.25 v dd positive supply voltage 0.8 v il v -4.75 -5.25 v ss negative supply voltage a input low voltage 550 950 780 i dd positive supply current v dd = 5.25v, v ss = -5.25v 320 650 performance guaranteed by supply rejection test performance guaranteed by supply rejection test pf 10 0.4 v dd - 0.5 v oh output high voltage input capacitance f xclk = 500khz, continuous-conversion mode a a i ss negative supply current v dd = 5.25v, v ss = -5.25v 1 20.48 41 0 i dd i lkg input leakage current xclk unloaded, continuous-conversion mode, rc oscillator operational (note 9) f xclk = 500khz, continuous-conversion mode (note 3) a 10 i lkg leakage current pf 10 output capacitance a 0.05 2 digital inputs at 0v or 5v power-down current dout, busy , v dd = 4.75v, i source = 1.0ma v dd = 5.25v, v ss = -5.25v, v xclk = 0v, pd = 1 v out = 5v or 0v (note 3) 10,240 clock-cycles/conversion dout, busy , i sink = 1.6ma conditions units min typ max symbol parameter ms 204.80 t conv synchronous conversion time (note 7) 102,400 clock-cycles/conversion mhz 0.25 1.25 f osc oversampling clock frequency (note 8) v 2.4 v ih input high voltage i ss v 0 3.0 v ref differential reference input voltage range pf 10 reference input capacitance (note 3) v 0.4 v ol output low voltage xclk, i sink = 200a v v dd - 0.5 xclk, v dd = 4.75v, i source = 200a na 500 i ref+ , i ref- reference input current v ref+ = 2.5v, v ref- = 0v v v ss +v dd - 2.25 2.25 v ref+ , v ref- absolute reference input voltage range conversion time digital outputs (dout, busy , and xclk when rcsel = v dd ) power requirements (all digital inputs at 0v or 5v) reference inputs digital inputs ( cs , sclk, din, and xclk when rcsel = 0v) downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 4 _______________________________________________________________________________________ electrical characteristicsmax111 (v dd = 5v 5%, f xclk = 1mhz, 2 mode (dv2 = 1), 81,920 clk cycles/conv, v ref+ = 1.5v, v ref- = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) lsb na 500 conditions i in+ , i in- input bias current (note 3) pf 10 -0.667 x v ref v in 0.667 x v ref -v ref v in v ref -0.667 x v ref v in 0.667 x v ref input capacitance -v ref v in v ref v 0v dd - 3.2 v in+ , v in- absolute input voltage range v -v ref +v ref v in differential input voltage range -v ref v in v ref ppm 15 v dd = 4.75v to 5.25v power-supply rejection %fsr inl ppm/c 8 full-scale error temperature drift relative accuracy, differential input (notes 3, 5C7) (notes 3, 4) 0.25 2 % 0.2 0.20 dnl differential nonlinearity (note 6) units min typ max symbol ppm/v 6 (note 2) parameter 14 + pol + ofl res resolution cmrr mv 4 offset error common-mode rejection ratio 10mv (v in+ = v in- ) 2.0v bits no-missing-codes resolution 0.10 (note 3) -8 0 0.05 0.10 full-scale error uncalibrated 0.03 0.05 max111bm 13 + pol + ofl bits 0.18 v in+ = v in- = 0v max111bc/e max111ac/e after gain calibration (note 5) v in 0.667 x v ref 0v v in v ref v in 0.667 x v ref 0v v in v ref 0v v in v ref v in 0.667 x v ref %fsr inl relative accuracy, single-ended input (in- = gnd) 0.25 0.15 0.10 0.1 0.06 max111bm 0.18 max111bc/e max111ac/e accuracy (note 1) analog inputs -0.667 x v ref v in 0.667 x v ref downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs _______________________________________________________________________________________ 5 electrical characteristicsmax111 (continued) (v dd = 5v 5%, f xclk = 1mhz, 2 mode (dv2 = 1), 81,920 clk cycles/conv, v ref+ = 1.5v, v ref- = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) v v v 4.75 5.25 v dd positive supply voltage 0.4 ms v ol 0.8 v il 204.80 output low voltage a input low voltage 640 1200 t conv synchronous conversion time (note 7) 102,400 clock-cycles/conversion xclk, i sink = 200a pf 10 reference input capacitance mhz 0.25 1.25 na f osc oversampling clock frequency (note 8) v 2.4 v ih input high voltage (note 3) v 0 1.5 v ref 960 i dd supply current v dd = 5.25v differential reference input voltage range performance guaranteed by supply rejection test 500 i ref+ , i ref- reference input current pf 10 v ref+ = 1.5v, v ref- = 0v 0.4 v 0v dd - 3.2 v ref+ , v ref- v dd - 0.5 v oh output high voltage input capacitance absolute reference input voltage range v v dd - 0.5 f xclk = 500khz, continuous-conversion mode a 1 xclk, v dd = 4.75v, i source = 200a 20.48 41 0 i dd i lkg input leakage current xclk unloaded, continuous-conversion mode, rc oscillator operational (note 9) (note 3) a 1 i lkg leakage current pf 10 output capacitance a digital inputs at 0v or 5v power-down current dout, busy , v dd = 4.75v, i source = 1.0ma v dd = 5.25v, v xclk = 0v, pd = 1 v out = 5v or 0v (note 3) 10,240 clock-cycles/conversion dout, busy , i sink = 1.6ma conditions units min typ max symbol parameter conversion time digital outputs (dout, busy , and xclk when rcsel = v dd ) power requirements (all digital inputs at 0v or 5v) reference inputs digital inputs ( cs , sclk, din, and xclk when rcsel = 0v) downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 6 _______________________________________________________________________________________ note 10: timing specifications are guaranteed by design. all input control signals are specified with t r = t f = 5ns (10% to 90% of +5v) and timed from a +1.6v voltage level. note 1: these specifications apply after auto-null and gain calibration. performance at power-supply tolerance limits is guaranteed by power-supply rejection tests. tests are performe d at v dd = 5v and v ss = -5v (max110). note 2: 32,768 lsbs cover an input voltage range of v ref (15 bits). an additional bit (ofl) is set for v in > v ref . note 3: guaranteed by design. not subject to production tes ting. note 4: dnl is less than 2 counts (lsbs) out of 2 15 counts (14 bits). the major source of dnl is noise , and this can be further improved by averaging. note 5: see 3-step calibration section in text. note 6: v ref = (v ref+ - v ref- ), v in = (v in1+ - v in1- ) or (v in2+ - v in2- ). the voltage is interpreted as negative when the voltage at the negative input terminal exceeds the voltage at the positive input terminal. note 7: conversion time is set by control bits conv1Cconv4. note 8: tested at clock frequency of 1mhz with the divide-b y-2 mode (i.e. oversampling clock of 500khz). see typical operating characteristics section for the effect of other clock frequencies. also read the clock frequency section. note 9: this current depends strongly on c xclk (see applications information section). timing characteristics (see figure 6) (v dd = 5v, v ss = -5v (max110), t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) mhz 1.1 3.0 max11_ bm rc oscillator frequency 1.3 2.8 max11_ _c/e 2.0 t a = +25c parameter symbol min typ max units 80 60 cs to sclk hold time (note 10) t csh 0 ns din to sclk setup time (note 10) t ds 100 ns din to sclk hold time (note 10) t dh 0 ns 100 60 80 cs to sclk setup time (note 10) t css 100 ns 120 sclk, xclk pulse width (note 10) t ck 160 ns 03 58 0 0 100 data access time (note 10) t da 0 120 ns 0 60 100 0 120 sclk to dout valid delay (note 10) t do 0 140 ns 35 80 bus relinquish time (note 10) t dh 120 ns max11_ bm max11_ _c/e t a = +25c max11_ bm max11_ _c/e conditions max11_ _c/e max11_ _c/e max11_ bm t a = +25c max11_ bm t a = +25c c load = 50pf t a = +25c c load = 50pf max11_ _c/e t a = +25c max11_ bm t a = +25c max11_ _c/e/m downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs _______________________________________________________________________________________ 7 -0.10 0 -0.05 0.05 0.10 -4 -2 0 2 4 m ax110 relative accuracy (-v ref < v in < v ref ) max110 toc01 v in (v) relative accurancy (% fsr) -40c t a +85c range of inl values (200 piece sample size) -0.10 0 -0.05 0.05 0.10 -4 -2 0 2 4 m ax110 relative accuracy (-0. 83 v ref < v in < 0. 83 v ref ) max110 toc02 v in (v) relative accurancy (% fsr) -40c t a +85c range of inl values (200 piece sample size) 0.07 0.06 0.05 max110-toc03 0.02 0.01 0 0 0.25 0.50 0.75 1.00 1.25 0.04 0.03 f osc (mhz) relative accuracy (% fsr) 1 mode 2 mode 4 mode v dd = 4.75v v ss = -4.75v t a = +85c m ax110 relative accuracy vs. oversam pling frequency (f osc ) 0.10 max110-toc04 0.04 0.02 0 -50 -25 0 25 50 75 100 0.08 0.06 temperature (c) relative accuracy (% fsr) m ax110 relative accuracy vs. tem perature 8 6 7 max110-toc05 3 2 0 0.25 0.50 0.75 1.00 1.25 4 5 f osc (mhz) power dissipation (mw) 4 mode 2 mode 1 mode m ax110 power dissipation vs. oversam pling frequency (f osc ) v dd = 5.25v v in = 0v t a = -40c __________________________________________typic a l o pe ra t ing cha ra c t e rist ic s (max110, v dd = 5v, v ss = -5v, v ref+ = 1.5v, v ref- = -1.5v, differential input (v in+ = -v in- ), f xclk = 1mhz, 2 mode (dv2 = 1), 81,920 clocks/conv, t a = +25c, unless otherwise noted.) downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 8 _______________________________________________________________________________________ ____________________________typic a l ope ra t ing cha ra c t e rist ic s (c ont inue d) (max111, v dd = 5v, v ref+ = 1.5v, v ref- = 0v, differential input (v in+ = -v in- ), f xclk = 1mhz, 2 mode (dv2 = 1), 81,920 clocks/conv, t a = +25c, unless otherwise noted.) 0.14 0.12 0.1 max110-toc08 0.04 0.02 0 0 0.25 0.50 0.75 1.00 0.08 0.06 f osc (mhz) relative accuracy (% fsr) 4 mode 2 mode 1 mode v dd = 4.75v t a = +85c m ax111 relative accuracy vs. oversam pling frequency (f osc ) 0.10 max110-toc09 0.04 0.02 0 -50 -25 0 25 50 75 100 0.08 0.06 temperature (c) relative accuracy (% fsr) m ax111 relative accuracy vs. tem perature 7 6 5 max110-toc10 2 1 0 0 0.25 0.50 0.75 1.00 1.25 4 3 f osc (mhz) power dissipation (mw) 4 mode 2 mode 1 mode m ax111 power dissipation vs. oversam pling frequency (f osc ) v dd = 5.25v v in = 0v t a = -40c 0.10 0.05 0 -0.05 -0.10 max110-toc6 v in (v) -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 m ax111 relative accuracy (-0. 667v ref < v in < 0. 667v ref ) relative accuracy (% fsr) 0.10 0.05 0 -0.05 -0.10 max110-toc7 v in (v) -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 m ax111 relative accuracy (-v ref < v in < v ref ) relative accuracy (% fsr) downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs _______________________________________________________________________________________ 9 _______________de t a ile d de sc ript ion the max110/max111 adc converts low-frequency analog signals to a 16-bit serial digital output (1 4 data bits, a sign bit, and an overrange bit) using a fir st-order sigma-delta loop (figure 1). the differential input volt- age is internally connected to a precision voltage- to- current converter. the resulting current is integra ted and applied to a comparator. the comparator output then drives an up/down counter and a 1-bit dac. whe n the dac output is fed back to the integrator input, the sigma-delta loop is completed. during a conversion, the comparator output is a v ref- to v ref+ square wave; its duty cycle is proportional to the magnitude of the differential input voltage app lied to the adc. the up/down counter clocks data in from the comparator at the oversampling clock rate and averages the pulse-width-modulated (pwm) square wave to produce the conversion result. a 16-bit sta tic shift register stores the result at the end of the conver- sion. figure 2 shows the adc waveforms for a differ en- tial analog input equal to 1/2 (v ref+ - v ref- ). the resulting comparator and 1-bit dac outputs are high for seven cycles and low for three cycles of the ov er- sampling clock. since the analog input signal is integrated over ma ny clock cycles, much of the signal and quantization n oise is attenuated. the more clock cycles allowed during each conversion, the greater the noise attenuation (see programming conversion time ). ___________________________________________________ ___________pin de sc ript ion clock input / rc oscillator output. ttl/cmos-compat ible oversampling clock input when rcsel = gnd. connects to the internal rc oscil lator when rcsel = v dd . xclk must be connected to v dd or gnd through a resistor (1m or less) when rc osc mode is selected. xclk 8 serial clock input. ttl/cmos-compatible clock input for serial-interface data i/o. sclk 9 busy output. goes low at conversion start, and retu rns high at end of conversion. busy 10 positive power-supply inputconnect to +5v v dd 6 rc select input. connect to gnd to select external clock mode. connect to v dd to select rc osc mode. xclk must be connected to v dd or gnd through a resistor (1m or less) when rc osc mode is selected. rcsel 7 positive reference input ref+ 3 negative reference input ref- 2 channel 1 positive analog input in1+ 1 function name ssop 6 7 8 4 5 3 2 pin 1 dip/so chip-select input. pull this input low to perform a control-word-write/data-read opera- tion. a conversion begins when cs returns high, provided no-op is a 1. see the sec- tion using the max110/max111 with spi, qspi, and microwi re serial interfaces. cs 11 9 serial data output. high-impedance when cs is high. dout 12 10 serial data input. see control register section. din 13 11 digital ground gnd 16 12 max110 negative power-supply inputconnect to -5v v ss channel 2 negative analog input in2- 18 14 channel 2 positive analog input in2+ 19 15 channel 1 negative analog input in1- 20 16 no connectthere is no internal connection to this pin n.c. 4, 5, 14, 15 max111 analog ground agnd 17 13 downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 10 ______________________________________________________________________________________ ove rsa m pling cloc k xclk internally connects to a clock-frequency divid er network, whose output is the adc oversampling clock , f osc . this allows the selected clock source (internal r c oscillator or external clock applied to xclk) to be divided by one, two, or four (see clock divider-ratio control bits ). figure 3 shows the two methods for providing the ov er- sampling clock to the max110/max111. in external- clock mode (figure 3a), the internal rc oscillator is disabled and xclk accepts a ttl/cmos-level clock to provide the oversampling clock to the adc. select external-clock mode (figure 3a) by connectin g rcsel to gnd and a ttl/cmos-compatible clock to xclk (see selecting the oversampling clock frequency ). in rc-oscillator mode (figure 3b), the internal rc oscil- lator is active and its output is connected to xclk (figure 1). select rc-oscillator mode by connecting rcsel to v dd . this enables the internal oscillator and connects it to xclk for use by the adc and external system components. minimize the capacitive loading on xclk when using the internal rc oscillator. differential analog input v ref+ dc level at 1/2 v ref v ref- v ref+ v ref- output from 1-bit dac oversampling clock max110 max111 figure 2. adc waveforms during a conversion figure 1. functional diagram in1+ in+ in- input mux in1- in2+ in2- ref+ gm ref- gm integrator up/down counter - dither generator serial shift register din sclk cs 16 16 16 16 control register dout busy rcsel xclk osc timer + control logic + clock generator divider network, divide by 1, 2, or 4 rc oscillator max110 max111 downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ______________________________________________________________________________________ 11 adc ope ra t ion the output data from the max110/max111 is arranged in twos-complement format (figures 4, 5). the sign bit (pol) is shifted out first, followed by the overran ge bit (or), and the 14 data bits (msb first) (see figure 6). the max110 operates from 5v power supplies and converts low-frequency analog signals in the 3v range when using the maximum reference voltage of v ref = 3v (v ref = v ref+ - v ref- ). within the 3v input range, greater accuracy is obtained within 2.5v (s ee electrical characteristics for details). note that a nega- tive input voltage is defined as v in- > v in+ . for the max110, the absolute voltage at any analog input pi n must remain within the (v ss + 2.25v) to (v dd - 2.25v) range. the max111 operates from a single +5v supply and converts low-frequency differential analog signals in the 1.5v range when using the maximum reference volt- age of v ref = 1.5v. as indicated in the electrical characteristics , greater accuracy is achieved within the 1.2v range. the absolute voltage at any analog inp ut pin for the max111 must remain within 0v to v dd - 3.2v. when v in- > v in+ the input is interpreted as negative. the overrange bit (ofl) is provided to sense when t he input voltage level has exceeded the reference volt age level. the converter does not saturate until the input voltage is typically 20% larger. the linearity is n ot guar- anteed in this range. note that the overrange bit w orks properly if the reference voltage remains within th e rec- ommended voltage range (see reference inputs ). if the reference voltage exceeds the recommended input range, the overrange bit may not operate properly. digit a l i nt e rfa c e st a rt ing a conve rsion data is transferred into and out of the serial i/o shift register by pulling cs low and applying a serial clock at sclk. this fully static shift register allows sc lk to range from dc to 2mhz. output data from the adc is clocked out on sclks falling edge and should be re ad on sclks rising edge. input data to the adc at din is clocked in on sclks rising edge. a new conversion begins when cs returns high, provided the msb in the input control word ( no-op ) is a 1 (see using the max110/max111 with microwire, spi, and qspi serial interfaces ). figure 6 shows the detailed serial- interface timing diagram. c c s s must remain high during the conversion (while busy remains low). bringing cs low during the conver- sion causes the adc to stop converting, and may result in erroneous output data. using the max110/max111 with spi, qspi, and microwire serial interfaces figure 7 shows the most common serial-interface con - nections. the max110/max111 are compatible with spi, qspi (cpha = 0, cpol = 0), and microwire serial-interface standards. xclk ttl/cmos rcsel gnd +5v -5v (0v) ( ) are for max111. v dd v ss (agnd) max110 max111 figure 3b. connection for internal rc-oscillator m odexclk connects to the internal rc oscillator. note, the p ull-up resistor is not necessary if the internal oscillator is neve r shut down. xclk rcsel 1m gnd +5v -5v (0v) v dd +5v v ss (agnd) max110 max111 ( ) are for max111. figure 3a. connection for external-clock mode downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 12 ______________________________________________________________________________________ output code +overflow transition -overflow transition pol ofl d13...d0 0 1 00 . . .000 1 1 00 . . .001 1 1 00 . . .000 1 1 00 . . .010 1 0 11 . . .111 v ref -1lsb input voltage (lsbs) - v ref 0 0 11 . . .111 0 0 11 . . .110 0 0 11 . . .101 0 0 11 . . .100 +overflow 0 0 00 . . .001 0 0 00 . . .001 0 0 00 . . .000 1 1 11 . . .111 1 1 11 . . .110 1 1 00 . . .011 -overflow figure 4. differential transfer function output code overflow transition pol ofl d13...d0 0 1 00 . . .000 0 0 00 . . .001 0 0 00 . . .000 0 0 00 . . .010 1 1 11 . . .111 v ref -1lsb input voltage (lsbs) 0123 0 0 11 . . .111 0 0 11 . . .110 0 0 11 . . .101 0 0 11 . . .100 +overflow 0 0 00 . . .011 figure 5. unipolar transfer function downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ______________________________________________________________________________________ 13 cs sclk t csh t css t ck t dh msb lsb t ds din dout busy t dh t ck t do t da pol ofl msb do end of conversion start of conversion figure 6. detailed serial-interface timing the adc serial interface operates with just sclk, d in, and dout (allow sufficient time for the conversion to complete between read/write operations). achieve co n- tinuous operation by connecting busy to an uncommit- ted p i/o or interrupt, to signal the processor wh en the conversion results are ready. figures 8a and 8b sho w the timing for spi/microwire and qspi operation. the fully static 16-bit i/o register allows infinit e time between the two 8-bit read/write operations necessa ry to obtain the full 16 bits of data with spi and microwire. cs must remain low during the entire two-byte transfer (figure 8a). qspi allows a full 16-bit data transfer (figure 8b). interfacing to the 80c32 microcontroller family figure 7c shows the general 80c32 connection to the max110/max111 using port 1. for a more detailed dis - cussion, see the max110 evaluation kit manual. i /o shift re gist e r serial data transfer is accomplished with a 16-bit fully static shift register. the 16-bit control word shif ted into this register during a data-transfer operation cont rols the adcs various functions. the msb ( no-op ) enables/disables transfer of the control word withi n the adc. a logic 1 causes the remaining 15 bits in the con- trol word to be transferred from the i/o register i nto the control register when cs goes high, updating the adcs configuration and starting a new conversion. if i/o sck miso mosi maskable interrupt ss a. spi/qspi +5v p cs sclk dout din busy max110 max111 i/o sk si so maskable interrupt or i/o b. microwire p cs sclk dout din busy p1.0 p1.1 p1.2 p1.3 p1.4 c. 80c51/80c32 p cs sclk din dout busy max110 max111 max110 max111 figure 7. common serial-interface connections downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 14 ______________________________________________________________________________________ busy 1 st byte read/write 2 nd byte read/write cs sclk dout pol ofl d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 no op nu nu conv4 conv3 conv2 conv1 dv4 dv2 nu nu chs cal nul pdx pd din max110 max111 figure 8a. spi/microwire-interface timing busy cs sclk dout pol ofl d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 no op nu nu conv4 conv3 conv2 conv1 dv4 dv2 nu nu chs cal nul pdx pd din max110 max111 figure 8b. qspi serial-interface timing downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ______________________________________________________________________________________ 15 no-op is a zero, the control word is not transferred to the control register, the adcs configuration remai ns unchanged, and no new conversion is initiated. this allows specific adcs in a daisy chain arrangement to be reconfigured while leaving the remaining adcs unchanged. table 1 lists the various adc control wo rd functions. output data is shifted out of dout at the same time the input control word for the next conversion is shift ed in (figure 8). on power-up, all internal registers reset to zero. therefore, when writing the first control word to t he adc, the data simultaneously shifted out will be ze ros. the first conversion begins when cs goes high ( no-op = 1). the results are placed in the 16-bit i/o regi ster for access on the next data-transfer operation. pow e r-dow n m ode bits 0 and 1 control the adcs power-down mode. if bit 0 (pd) is a logic high, power is removed from all a nalog circuitry except the rc oscillator. a logic high at bit 1 (pdx) removes power from the rc oscillator. if both bits pd and pdx are a logic high, or if pd is high and rcsel is low, the supply currents reduce to 4a. if an external xclk clock continues to run in power-down mode, the supply current will depend on the clock r ate. when pdx is set high, the internal rc oscillator st ops shortly after cs returns high. if the next control word written to the device has no-op = 1 instructing the adc to convert, busy will go low, but because the r c oscillator is stopped, busy will remain low and wil l not allow a new conversion to begin. to avoid this situ ation, write a dummy control word with no-op = 0 and any combination of bits 14-0 in the control word follow ing the control word with pdx = 0. with no-op = 0, bits 14- 0 are ignored and the internal state machine resets . next, perform a normal 3-step calibration (see tabl e 3). note that xclk must be connected to v dd or gnd through a resistor (suggested value is 1m ) when the rc oscillator mode is selected (rcsel = v dd ). this resistor is not necessary if the external oscillato r mode is used, or if the internal oscillator is not shut down. se le c t ing t he ana log i nput s bit 4 (chs) controls which of the two differential inputs connect to the internal adc inputs (see the functional diagram ). a logic high selects in2+ and in2- while a logic low selects in1+ and in1-. table 2 shows the allowable input multiplexer configurations. table 1. input control-word bit map first bit clocked in. pd pdx nul cal chs nu nu dv2 dv4 conv1 conv2 conv3 conv4 nu nu no-op 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 analog power-down. set this bit high to power down the analog section. pd 0 oscillator power-down. set this bit high to power d own the rc oscillator. pdx 1 internal offset-null bit. a logic high selects offs et-null mode. see table 3. nul 2 gain-calibration bit. a logic high selects gain-cal ibration mode. see table 3. cal 3 input channel select. a logic high selects channel 2 (in2+ and in2-), while a logic low selects channel 1 (in1+ and in1-). see tables 2 and 3. chs 4 xclk to oversampling cock ratio control bits. see t able 5. dv2, dv4 7, 8 conversion time control bits. see table 4. conv1Cconv4 9C12 used for test purposes only. set these bits low. nu 5, 6, 13, 14 if this bit is a logic high, the remaining 15 lsbs are transferred to the control register and a new conversion begins when cs returns high. if this bit is set low, the control w ord is not passed to the control register, the adc configurati on remains unchanged, and no new con- version begins when cs returns high. no-op 15 description name bit downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 16 ______________________________________________________________________________________ x = don't care table 3. procedure to calibrate the adc 0 0 1 0 0 or 1 00 xx no change 00 1 performs an offset-null conversion with the internal adc inputs shorted to the selected input channel's negative input (in1- or in2-). the next operation performs the first signal conversion with the new setup. 3 0 0 0 1 x 00 xx no change 00 1 performs a gain-calibration conversion with the null register contents as the starting value. the result is stored in the calibration register. 2 0 0 1 1 x 00 xx new data 00 1 sets the new conversion speed (if required) and performs an offset correction conversion with the internal adc inputs shorted to ref-. the result is stored in the null register. (this step also selects the speed/resolution for the adc.) 1 pd pdx nul cal chs not used dv2 & dv4 conv1- conv4 not used n n o o - - o o p p description step control word x = don't care table 2. allowable input multiplexer configurations input control word is not transferred to the contro l register. adc configuration remains unchanged and no new conversi on starts when cs returns high. no change no change 0 x x x ref+ and ref- connected to the adc inputs; gain-cal ibration mode selected. autocal conversion begins when cs returns high, and the results are stored in the 16-bit i/o register. ref- ref+ 1 x 0 1 ref- connected to the adc inputs; offset-null mode selected. autonull conversion begins when cs returns high, and the results are stored in the nul l register. ref- ref- 1 x 1 1 in2- connected to the adc inputs; offset-null mode selected. autonull conversion begins when cs returns high, and the results are stored in the nul l register. in2- in2- 1 1 1 0 in1- connected to the adc inputs; offset-null mode selected. autonull conversion begins when cs returns high, and the results are stored in the nul l register. in1- in1- 1 0 1 0 channel 2 connected to adc inputs. conversion begin s when cs returns high. in2- in2+ 1 1 0 0 channel 1 connected to adc inputs. conversion begin s when cs returns high. in1- in1+ 1 0 0 0 description adc in- adc in+ n n o o - - o o p p chs nul cal downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ______________________________________________________________________________________ 17 3 -st e p ca libra t ion the data sheet electrical specifications apply to t he device after optional calibration of gain error and offset. uncalibrated, the gain error is typically 2%. table 3 describes the three steps required to calib rate the adc completely. once the adc is calibrated to the selected channel, set cal = 0 and nul = 0 and leave chs unchanged in the next control word to perform a signal conversion on the selected analog input channel. calibrate the adc after the following operations: when power is first applied if the reference common-mode voltage changes if the common-mode voltage of the selected input channel varies significantly. the cmrr of the analo g inputs is 0.25lsb/v. after changing channels (if the common-mode volt- ages of the two channels are different) after changing conversion speed/resolution. after significant changes in temperature. the offse t drift with temperature is typically 0.003v/c. automatic gain calibration is not allowed in the102,400 cycles per conversion mode (see programming conversion time ). in this mode, calibra- tion can be achieved by connecting the reference vo lt- age to one input channel and performing a normal conversion. subsequent conversion results can be co r- rected by software. do not issue a n n o o - - o o p p command directly following the gain calibration, as the cali- bration data will be lost. progra m m ing conve rsion t im e the max110/max111 are specified for 12 bits of accu - racy and up to 14 bits of resolution. the adcs re solu- tion depends on the number of clock cycles allowed during each conversion. control-register bits 9C12 (conv1Cconv4) determine the conversion time by controlling the nominal number of oversampling cloc k cycles required for each conversion (oscc/conv). table 4 lists the available conversion times and re sult- ing resolutions. to program a new conversion time, perform a 3-step calibration with the appropriate conv1Cconv4 data used in table 3. the adc is now calibrated at the n ew conversion speed/resolution. table 4. available conversion times * gain-calibration mode is not available with 102,4 00 clock cycles/conversion selected. clock duty cycles of 50% 10% are recommended. table 5. clock divider-ratio control conv4 conv3 conv2 conv1 clock cycles per conversion nominal conversion time rcsel = gnd, dv2 = dv4 = 0, xclk = 500khz (ms) conversion resolution (bits) 1 0 0 1 10,240 20.48 12 + pol 0 0 1 1 20,480 40.96 13 + pol 0 1 1 0 81,920 163.84 14 + pol 0 0 0 0 102,400* 204.80 14 + pol not allowed 1 1 xclk or internal rc oscillator is divided by 2 and connects to the adc; f osc = f xclk 2. 0 1 xclk or internal rc oscillator is divided by 4 and connects to the adc; f osc = f xclk 4. 1 0 xclk or internal rc oscillator connects directly to the adc; f osc = f xclk . 0 0 description dv4 dv2 downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 18 ______________________________________________________________________________________ se le c t ing t he ove rsa m pling cloc k fre que nc y choose the oversampling frequency, f osc , carefully to achieve the best relative-accuracy performance from the max110/max111 (see typical operating characteristics ). clock divider-ratio control bits bits 7 and 8 (dv2 and dv4) program the clock- frequency divider network. the divider network sets the frequency ratio between f xclk (the frequency of the external ttl/cmos clock or internal rc oscillator) and f osc (the oversampling frequency used by the adc). an oversampling clock frequency between 450khz and 700khz is optimum for the converter. best perfor- mance over the extended temperature range isobtained by choosing 1mhz or 1.024mhz with the divide-by-2 option (dv2 = 1) (see the section effect of dither on inl ) . to determine the converters accura- cy at other clock frequencies, see the typical operating characteristics and table 5. effect of dither on relative accuracy first-order sigma-delta converters require dither f or randomizing any systematic tone being generated in the modulator. the frequency of the dither source p lays an important role in linearizing the modulator. the ratio of the dither generators frequency to that of the modu- lators oversampling clock can be changed by settin g the dv2/dv4 bits. the xclk clock is directly used b y the dither generator while the dv2/dv4 bits reduce the oversampling clock by a ratio of 2 or 4. over the c om- mercial temperature range, any ratio (i.e., 1, 2, o r 4) between the dither frequency and the oversampling clock frequency can be used for best performance. over the extended and military temperature ranges, the ratio of 2 or 4 gives the best performance. see the typical operating characteristics to observe the effect of the clock divider on the converters linearity. 5 0 h z/6 0 h z line fre que nc y re je c t ion high rejection of 50hz or 60hz is obtained by using an oversampling clock frequency and a clock-cycles/con - version setting so the conversion time equals an in te- gral number of line cycles, as in the following equ ation: f osc = f line x m / n where f osc is the oversampling clock frequency, f line = 50hz or 60hz, m is the number of clock cycles per conversion (see table 4), and n is the number of li ne cycles averaged every conversion. this noise rejection is inherent in integrating and sigma-delta adcs, and follows a sin(x) / x function (figure 9). notches in this function represent extr emely high rejection, and correspond to frequencies with an integral number of cycles in the max110/max111s selected conversion time. the shortest conversion time resulting in maximum simultaneous rejection of both 60hz and 50hz line f re- quencies is 100ms. when using the max111, use a 200ms conversion time for maximum 60hz and 50hz rejection and optimum performance. for either device, select the appropriate oversampling clock frequency and either an 81,240 or 102,400 clock cycles per co n- version (ccpc) ratio. table 6 suggests the possible configurations. 0 -10 -20 -30 -40 -50 -60 0.1 1 conversion time line cycle period signal frequency in hz for 100ms conversion time (see table 6) 1 10 20 30 40 50 60 70 80 90 100 2345678910 gain (db) figure 9. max110/max111 noise rejection follows si n(x) / x function downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ______________________________________________________________________________________ 19 a 100ms conversion time cannot be achieved with eit her 10,240 ccpc or 20,480 ccpc modes because f osc would be below the minimum 250khz requirement. when the gain calibration is performed, the convers ion times change approximately 1% to compensate for the modulators gain error. this slightly degrades the line- frequency rejection, because the corrected conversi on time is no longer an exact multiple of the line fre quency. typically, the rejection of 50hz/60hz from the conv erter is 55db; i.e., if there is 100mv injection at the r eference or the analog input pin, it will cause an uncertain ty of 0.006%. if the system has large 50hz/60hz noise, t he use of internal auto gain calibration is not recomm end- ed. instead, gain calibration should be done off-ch ip, using numerical computation methods. if you wish to use a configuration other than those sug- gested in table 6, you can accomplish similar 50hz and 60hz line-frequency rejection off-chip by avera g- ing several conversions. __________applic a t ions i nform a t ion la yout , grounding, bypa ssing for minimal noise, bypass each supply to gnd with a 0.1f capacitor. a ground plane should also be plac ed under the analog circuitry. to minimize the couplin g effects of stray capacitance, keep digital lines as far from analog components and lines as possible. figur e 10 shows the suggested power-supply and ground- plane connections. *r = 10 *optional digital circuitry power supplies v dd v ss +5v dgnd +5v -5v gnd gnd 4.7 f 0.1 f 0.1 f 4.7 f max110 figure 10a. max110 power-supply grounding connecti ons *r = 10 *optional digital circuitry power supplies v dd agnd +5v dgnd +5v gnd gnd 4.7 f 0.1 f max111 figure 10b. max111 power-supply grounding connecti ons ccpc = clock cycles per conversion table 6. suggested xclk frequencies to achieve maximum rejection of both 50hz/60hz linefrequencies max111 (t convert = 200ms) 81,240 ccpc 102,400 ccpc divider ratio f xclk (mhz) relative accuracy (%) f xclk (mhz) relative accuracy (%) 1:1 0.4062 0.030 0.512 0.030 2:1 0.8124 0.025 1.024 0.025 4:1 1.6248 0.022 2.048 0.023 max110 (t convert = 100ms) 81,240 ccpc 102,400 ccpc divider ratio f xclk (mhz) relative accuracy (%) f xclk (mhz) relative accuracy (%) 1:1 0.8124 0.025 1.024 0.065 2:1 1.6248 0.018 2.048 0.045 4:1 3.2496 0.016 4.096 0.030 downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 20 ______________________________________________________________________________________ capacitive loading effects of xclk in internal rc-oscillator mode when using the internal rc oscillator, capacitive l oad- ing effects on the xclk pin must be minimized. stra y capacitance causes the v dd power consumption to increase by an amount p = 1 M 2 cv 2 f, where c = stray capacitance, v is the supply voltage, and f is the fre- quency of the internal rc oscillator. ex t e rna l re fe re nc e the reference inputs to the adc are high impedance, allowing both an external voltage reference and rat io- metric applications without loading effects. the fu lly dif- ferential analog signal and reference inputs are advantageous for performing ratiometric conversions (figures 11 and 12). for example, when measuring load cells, the bridge excitation and the adc refer ence input both share the same voltage source. as the ex ci- tation changes with temperature or voltage, the out put of the load cell will change. but since the differe ntial reference voltage also changes, the conversion resu lts remain constant, all else remaining equal. we igh sc a le applic a t ion the fully differential analog signal and reference inputs make the max111 easy to interface to transducers wi th differential outputs, such as the load cell in figu re 11. because the adc input is differential, the load cel l only requires differential gain, eliminating the need fo r the difference amplifier (differential to single-ended con- verter) of the standard three op-amp instrumentatio n- amplifier realization. the 30mv full-scale bridge output is amplified to 2 v full-scale and applied to the max111 channel-one input. the reference voltage to the adc is created by a voltage divider connected to the +5v rail. the same 5v provides excitation for the bridge; therefore, as t he excitation voltage varies, the reference voltage to the adc also varies, providing an adc output that does not depend on the supply voltage. the two 121k resistors connected to the +5v supplies shift the common-mode voltage from 2.5v (5v/2) to 1.5v to ensure linearity. match these two resistors to avoid introducing differential offset, or trim the resistor mismatch with a potentiometer. in practice, the sca le is zeroed or tared by storing the average of sever al conversions in a memory location while the scale is +5v 30mv full-scale 121k 2k 121k 49.9k 1k 22k 10k 1k 1k 1/2 max492 1/2 max492 1f 1f ref+ ref- in1+ in1- agnd cs din dout sclk 49.9k v dd +5v 0.1f max111 +5v +5v +5v gnd figure 11. weigh scale application downloaded from: http:///
unloaded, and subtracting this value from actual we ight measurements. the lowpass filtering action of the max111s sigma-delta converter helps minimize noise . the resolution of the weigh scale can be further increased by averaging several conversions. t he rm oc ouple circ uit w it h soft w a re com pe nsa t ion a thermocouple is created by the junction of dissim ilar metals, and generates a voltage proportional to tem per- ature (seebeck voltage), making it useful for tempe ra- ture-measurement instruments. when a thermocouple probe is connected to a measurement instrument, oth er thermoelectric potentials are created between the a lloys of the probe and the copper connectors of the instr u- ment. these potentials introduce a temperature-depe n- dent error that must be subtracted from the tempera ture measurement to obtain an accurate result. according to the law of intermediate metals, the junction of the ther- mocouple-probe alloys with the copper of the instru ment junction block can be treated as another thermocoup le of the same type. the voltage measured by the instr u- ment can be expressed as: v = (t1 - t ref ) where is the seebeck constant for the type of thermo- couple, t1 is the temperature being measured, and t ref is the temperature of the junction block. although one method to obtain t ref is to force the junction block to a known temperature (0c), a more popular approach is to measure t ref directly using a thermistor or pn junction voltage. the circuit in figure 12 shows a k-type thermocoupl e going through a 54db gain stage to channel 1 of the max110. a max874 voltage reference provides both the 3v reference voltage and reference junction tem - perature information to the max110. armed with the temperature information provided by the max874, the thermocouple voltage created at the junction block can be subtracted out in software. the temp output of t he max874 is nominally 690mv at room temperature, and increases with temperature at about 2.3mv/c. place the max874 as close as possible to the terminal blo ck, and ensure good thermal contact between them. this circuit employs a common k-type thermocouple and, with the component values shown, can indicate tem- peratures in the range of -150c to +125c. m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ______________________________________________________________________________________ 21 243k 1k 1k 10k 1f 1f in1+ in1- ref- ref+ v ss -5v cs din dout sclk 243k 1m 1k 10k 10k k-type v dd +5v in2- in2+ max110 1/4 max479 1/4 max479 1/4 max479 temp out v in max874 +5v figure 12. thermocouple circuit with software comp ensation downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs 22 ______________________________________________________________________________________ top view 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 in1+ ref- ref+ n.c. n.c. v dd rcsel xclk in1- in2+ in2- v ss (agnd) gnd n.c. n.c. din 9 10 12 11 sclk busy dout cs max110 max111 ssop ( ) are for max111 ____pin configura t ions (c ont inue d) _orde ring i nform a t ion (c ont inue d) __________________chip topogra phy transistor count: 5849 substrate connected to v dd v ss (agnd) rcsel ref+ dout xclk 0. 168" (4. 27mm) 0. 121" (3. 07mm) sclk busy cs din v ss (agnd) gnd gnd ref- in1+ in1- in2+ in2- v dd v dd ( ) are for max111 0.05 16 plastic dip -40c to +85c max110bepe 0.05 0.05 0.03 0.05 0.03 0.03 inl(%) 16 cerdip** -55c to +125c max110bmje 20 ssop -40c to +85c max110beap 20 ssop -40c to +85c max110aeap 16 wide so 16 wide so 16 plastic dip pin-package temp. range -40c to +85c -40c to +85c -40c to +85c max110bewe max110aewe max110aepe part max111 acpe 0c to +70c 16 plastic dip 0.03 max111bcpe 0c to +70c 16 plastic dip 0.05 max111acwe 0c to +70c 16 wide so 0.03 max111bcwe 0c to +70c 16 wide so 0.05 max111acap 0c to +70c 20 ssop 0.03 max111bcap 0c to +70c 20 ssop 0.05 max111bc/d 0c to +70c dice* 0.05 max111aepe -40c to +85c 16 plastic dip 0.03 max111bepe -40c to +85c 16 plastic dip 0.05 max111aewe -40c to +85c 16 wide so 0.03 MAX111BEWE -40c to +85c 16 wide so 0.05 max111aeap -40c to +85c 20 ssop 0.03 max111beap -40c to +85c 20 ssop 0.05 max111bmje -55c to +125c 16 cerdip** 0.05 * contact factory for dice specifications. ** contact factory for availability. downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ______________________________________________________________________________________ 23 ___________________________________________________ ____pa c k a ge i nform a t ion pdipn.eps soicw.eps downloaded from: http:///
m ax 1 1 0 /m ax 1 1 1 low -cost , 2 -cha nne l, 1 4 -bit se ria l adcs ___________________________________________pa c k a ge i nform a t ion (c ont inue d) cdips.eps maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 24 ____________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ? 1998 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. ssop.eps downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX111BEWE

	To Download MAX111BEWE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .